Accompanying the miniaturization and performance enhancement of electronic equipment in recent years, the number of pins in a semiconductor element included in the electronic equipment increases and various types of electronic components constituting the electronic equipment become smaller. Accordingly, there has been a dramatic increase in the number and density of wirings in a printed board on which they are mounted. In particular, the number of leads led out from the semiconductor element (semiconductor chip) and the number of terminals have increased rapidly, so that the printed board (wiring board) becomes increasingly finer. Consequently, fine pitch connection techniques are gaining greater importance.
The fine pitch connection techniques can be divided broadly into a wire bonding (WB) method, a flip chip bonding (FC) method, and a tape automated bonding (TAB) method, each of which will be described briefly in the following.
According to the wire bonding (WB) method, electrodes of a semiconductor chip and electrodes of a lead frame are connected to each other mainly using gold wires (diameter: 20 to 25 μm). The connection is achieved through solid phase diffusion caused by applying heat or ultrasonic waves to the gold wires and the electrodes of both the semiconductor chip and the lead frame. The WB method is disclosed in Patent Document 1, for example. According to the flip chip bonding (FC) method, bumps (protruding electrodes) are formed on a semiconductor chip, and these bumps are connected to electrodes on a wiring board. The FC method is characterized in that it provides a configuration in which a surface on which the electrodes are formed (hereinafter, referred to simply as an “electrode-formed surface”) of the semiconductor chip and an electrode-formed surface of the wiring board face each other. The FC method is disclosed in Patent Document 2, for example. According to the TAB method, semiconductor chips first are connected to a long tape provided with lead wirings. The chip provided with the lead then is punched out from the tape, and the lead is connected to a substrate. Basically, the TAB method is carried out automatically through a reel-to-reel process. The TAB method is disclosed in Patent Document 3, for example.
Patent Document 1: JP 4(1992)-286134 A
Patent Document 2: JP 2000-36504 A
Patent Document 3: JP 8(1996)-88245 A
The WB method disclosed in Patent Document 1 will be described with reference to FIGS. 21A and 21B. FIG. 21A is a top view showing the wire-bonded state, and FIG. 21B is a cross-sectional view taken along a line I-I in FIG. 21A.
According to the WB method, a semiconductor chip 501 is die-bonded to a portion (a die pad) of a lead frame 504, and then wire bonding pads 502 of the semiconductor chip 501 and external terminals 505 (inner lead portions) of the lead frame 504 are wire-bonded using bonding wires 503. Thereafter, a region including the semiconductor chip 501 and the inner lead portions of the external terminals 505 is encapsulated with an encapsulation resin 506, whereby, for example, a resin-encapsulated body (a semiconductor module) 500 as shown in FIG. 22 is obtained. The external terminals 505 exposed from the encapsulation resin 506 are connected to a wiring board (not shown), whereby the semiconductor chip 501 is connected electrically to the wiring board.
However, the WB method has the following problems. First, there is a problem in that a mounting area of a semiconductor element component (here, this refers to the module 500 including the semiconductor chip 501) is large. That is, in the WB method, since the semiconductor chip 501 is not mounted on the wiring board directly but is connected to the external terminals 505 of the lead frame 504 via the bonding wires 503, it is inevitable that the size of the semiconductor module 500 (the element size or the component side) becomes larger than that of the semiconductor chip 501. Consequently, the mounting area of the semiconductor module 500 becomes large.
Furthermore, since the wire bonding pads 502 of the semiconductor chip 501 and the external terminals 505 of the lead frame 504 are connected to each other one by one with the bonding wires 503, there is a problem in that, as the number of the terminals increases, the time and effort required for the operation increase. Moreover, the pitch of the external terminals 505 on the lead frame 504 defines the pitch of the semiconductor element 500, thus imposing limitations on the narrowing of the pitch.
Next, the FC method disclosed in Patent Document 2 will be described with reference to FIG. 23. FIG. 23 shows a cross-sectional configuration of a semiconductor device 600 mounted by the FC method.
According to the FC method, electrodes 604 of a semiconductor chip 605 are connected to wiring patterns 602 provided on a substrate 601 via bumps 603. More specifically the electrodes 604 of the semiconductor chip 605 that has a sensitive area 606 in which a transistor etc. are formed are connected to the predetermined wiring patterns 602 provided on the substrate 601 via the bumps 603, whereby the semiconductor chip 605 is mounted on the substrate 601 with a space being formed therebetween. Thereafter, an encapsulation resin 607 is formed by inserting resin into the space between the substrate 601 and the semiconductor chip 605 so as to embed the wiring patterns 602, the bumps 603, and the electrodes 604 in the resin. The semiconductor device 600 for which the FC method is employed is configured as above.
However, the FC method has the following problems. First, there is a problem in that aligning the semiconductor chip 605 is difficult. According to the FC method, since the semiconductor chip 605 is mounted on the substrate 601 with its electrode-formed surface facing downward, the bumps 603 of the semiconductor chip 605 cannot be seen directly from the outside. This makes the alignment very difficult. Moreover, the pitch of the electrodes 604 of the semiconductor chip 605 when the FC method is employed is narrower than the pitch of the external terminals 505 when the WB method is employed. This factor also makes the alignment difficult.
Also, there is a problem in that the substrate 601 is liable to be expensive. The reason for this is that, according to the FC method, the substrate 601 is required to have the wiring patterns 602 that are fine patterns corresponding to the pitch of the electrodes 604 of the semiconductor chip 605. Another reason is that, when the electrodes 604 of the semiconductor chip 605 are arranged in an area array form, the substrate 601 is liable to have a multilayer structure. Moreover, when the FC method is employed, the semiconductor chip 605 is connected to the substrate 601 via the bumps 603. Thus, unless the coefficient of linear expansion of the semiconductor chip 605 is made as close as possible to the coefficient of linear expansion of the substrate 601, a stress is applied to the bumps 603 etc. Therefore, it is necessary to match the coefficients of linear expansion of both the semiconductor chip 605 and the substrate 601, and the matching of the coefficients of linear expansion needs to be performed strictly. In this respect, the cost of the substrate 601 increases.
Moreover since the semiconductor chip 605 is connected to the substrate 601 via the bumps 603, the heat dissipation is deteriorated. More specifically, since the semiconductor chip 605 is disposed on the substrate 601 with points thereof being in contact with the substrate 601 rather than the surface thereof being in contact with the substrate as in the case of the WB method, the heat dissipation is deteriorated. Also, in the first place, forming the bumps 603 takes time and effort.
Next, the TAB method disclosed in Patent Document 3 will be described with reference to FIGS. 24 and 25. FIG. 24 shows a cross-sectional configuration of a semiconductor device 700 for which the TAB method is employed, and FIG. 25 shows a configuration in which this semiconductor device 700 is mounted on a mounting board 709.
The semiconductor device 700 shown in FIG. 24 includes a base film 702 of a film carrier tape and a semiconductor IC chip 701 arranged in a device hole 702b provided in the base film 702. Copper foil wirings 703 are formed on the base film 702, and electrodes 701a of the semiconductor IC chip 701 are connected to inner leads 703a provided in inner end portions of the copper foil wirings 703. Lands 703b for external connection are provided at portions of the copper foil wirings 703 on the outer side relative to the inner leads 703a, and solder bumps 706 are formed on the lands 703b. Through holes 702a are provided in the base film 702. At the center of each of the lands 703b, a pore 703c is provided. A cover resist 704 is formed on the film carrier tape excluding the portions where the lands 703b are formed. An encapsulation resin 705 for protecting the semiconductor IC chip 701 is provided in the device hole 702b. 
In this semiconductor device 700, the solder bumps 706 serve as outer leads, and as shown in FIG. 25, the solder bumps 706 are connected to pads 709a on the mounting board 709. The semiconductor device 700 for which the TAB method is employed is mounted on the mounting board 709 by a mass reflow process.
However, the TAB method has the following problems. First, since an inner lead bonding (ILB) step and an outer lead bonding (OLB) step are separate steps, it takes time and effort to perform the TAB method. More specifically, in the example shown in FIG. 24, the step of connecting the inner leads 703a to the electrodes 701a of the semiconductor IC chip 701 and the step of forming the solder bumps 706 at the lands 703b are different types of steps, which complicates the operation. Furthermore, it is also necessary to encapsulate the semiconductor IC chip 701 arranged in the device hole 702b with the encapsulation resin 705, which also takes time and effort. In addition, there is a different type of problem in that, because the base film 702 having a larger area than the semiconductor IC chip 701 is used, the mounting area increases.